Nanoscale , 2014, Accepted Manuscript
DOI: 10.1039/C3NR06904D, Paper
DOI: 10.1039/C3NR06904D, Paper
Hongming Lv, Huaqiang Wu, Jinbiao Liu, Can Huang, Junfeng Li, Jiahan Yu, Jiebin Niu, Qiuxia Xu, Zhiping Yu, He Qian
CMOS compatible 200mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in...
The content of this RSS Feed (c) The Royal Society of Chemistry
CMOS compatible 200mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in...
The content of this RSS Feed (c) The Royal Society of Chemistry
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